Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 45195).
All users are now required to manually set the top-level RTL parameter CPT_CLK_CQ_ONLY=TRUE to enable a more reliable read data capture scheme; see (Xilinx Answer 53053). However, when Synplify is used a latch is being inferred for the init state machine output "wrcal_en" which causes the wrong write calibration triggers sent to the PHY. The inferred latch causes write calibration failures in hardware.
To work around this issue, a small change to the "qdr_phy_write_init_sm.v" module is necessary whichis included ina drop-in replacement patch attached at the end of this answer record.
To install the patch, extract the contents of "AR53136.zip" to the ./user_design/rtl/phy directory of the generated MIG 7 Series design (example: C:\my_ddr_design\user_design\rtl\phy).
11/27/2012 - Initial release
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