Version Found: 1.7
Version Resolved: See (Xilinx Answer 45195)
If implementing the MIG 7 Series DDR3 v1.7 design, timing violations might be seen in the OCLKDELAY calibration module. This answer record details why these violations occur and indicates the work-around.
| AR# 53434 | |
|---|---|
| Date | 01/31/2013 |
| Status | Active |
| Type | Known Issues |
| Devices |
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| IP |
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