AR# 54482


IP Release Notes and Known Issues for LogiCORE IP LTE Fast Fourier Transform core for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the LogiCORE IP LTE Fast Fourier Transform core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE IP LTE Fast Fourier Transform core IP Page:


General Information

Supported Devices can be found in the following three locations:
  For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Core Version Vivado Tools Version
v2.0(Rev. 6) 2014.4
v2.0(Rev. 5) 2014.3
v2.0(Rev. 5) 2014.2
v2.0(Rev. 4) 2014.1
v2.0(Rev. 3) 2013.4
v2.0(Rev. 2) 2013.3
v2.0(Rev. 1) 2013.2
v2.0 2013.1

General Guidance
The table below provides answer records for general guidance when using the LogiCORE IP LTE Fast Fourier Transform core.
Answer Record Title

Known and Resolved Issues
The following table provides known issues for the LogiCORE IP LTE Fast Fourier Transform core, starting with v2.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Answer Record Title Version Found Version Resolved
(Xilinx Answer 63525) The overflow flag is not asserted when it occurs v2.0(Rev. 6) N/A
(Xilinx Answer 61375) The IP outputs incorrect results when running behavioral simulation with VCS-MX I-2014.03 or VCS-MX I-2014.03-2. v2.0(Rev.5) N/A
(Xilinx Answer 55109) Why is there a mismatch between C model and HDL on the overflow output when using the Pipelined, Streaming I/O architecture with user-defined scaling? v1.0 N/A 
(Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>? v1.0 v2.0

Revision History
02/11/2015 - Added v2.0(Rev. 5) and v2.0(Rev. 6) to Version Table and (Xilinx Answer 63525)
07/07/2014 - Added v2.0(Rev. 4) and v2.0(Rev. 5) to Version Table and (Xilinx Answer 61375)
04/03/2013 - Initial release

Linked Answer Records

Child Answer Records

AR# 54482
Date 03/23/2015
Status Active
Type Release Notes
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