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  3. AR# 54550: LogiCORE IP MIPI D-PHY Controller - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions

AR# 54550

LogiCORE IP MIPI D-PHY Controller - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions

Description

This answer record contains the Release Notes and Known Issues for the MIPI D-PHY Controller Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

LogiCORE MIPI D-PHY Controller Core IP Page:

https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html

Solution

General Information

Supported Devices can be found in the following three locations:


For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Changelog included with the core in Vivado.
  • Subsystem or IP - Click on the Changelog links below.
  • Standalone Software Drivers - See the Chagelog included with the Doxygen Drivers in the Xilinx SDK
  • Standalone Software Drivers - Github Software Driver Repo


Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version IP ChangelogIP Patches
v4.12018.1
v4.0 (Rev. 1)2017.4(Xilinx Answer 70386)(Xilinx Answer 70431)
v4.02017.3(Xilinx Answer 69903)(Xilinx Answer 70195)
v3.1 (Rev.1)2017.2(Xilinx Answer 69326)(Xilinx Answer 69760)
v3.12017.1(Xilinx Answer 69055)(Xilinx Answer 69273)
v3.0 (Rev. 1)2016.4(Xilinx Answer 68369)(Xilinx Answer 68810)
v3.02016.3(Xilinx Answer 68021)
v2.0 (Rev. 1)2016.2(Xilinx Answer 67345)
v2.02016.1(Xilinx Answer 66930)
v1.02015.3(Xilinx Answer 65570)

General Guidance

The table below provides Answer Records for general guidance when using the LogiCORE MIPI D-PHY Controller core.

Article NumberArticle Title
(Xilinx Answer 67249)What is the maximum value of start-up time before High-speed data transfer?
(Xilinx Answer 66088)Are there plans to support MIPI D-PHY v1.2?

Known and Resolved Issues

The following table provides known issues for the MIPI D-PHY Controller core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 70591)Can we changes IDELAY tap values on the fly for MIPI D-PHY IP v4.0 ? (IP targeting 7 Series devices)v4.0v4.1
(Xilinx Answer 70581)Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices v4.0 (Rev. 1)v4.1
(Xilinx Answer 70196)On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRLv4.0v4.0 (Rev. 1)
(Xilinx Answer 69671)When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission?v3.1 (Rev. 1)v4.0
(Xilinx Answer 69931)When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1?v3.1 (Rev. 1)N/A
(Xilinx Answer 69766)When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes when targeting 7 Series devices?v3.1 (Rev. 1)N/A
(Xilinx Answer 67365)What is the behavior of receiver IP on SoT pattern and why do I not see an error when sending "BC" and receiving "B8"?v2.0v3.0
(Xilinx Answer 69274)Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY Controller RX?v3.1N/A
(Xilinx Answer 69057)Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 RX Subsystem?v3.0 (Rev. )v3.1
(Xilinx Answer 68603)Slave Mode (Shared logic in example design) D-PHY RX IP does not work when it is sharing resources with Master mode (Shared Logic in core) D-PHY RX IPv3.0 (Rev .1)v3.1
(Xilinx Answer 68603)Why does the Slave IP not work after updating to 2016.4? v3.0 (Rev. 1)3.0 (Rev. 1)N/A
(Xilinx Answer 67296)Are multi-lane use cases supported in MIPI D-PHY IP? v2.0N/A
(Xilinx Answer 67258)Why is there a change to the rxvalidhs behavior when receiving in high-speed mode?v1.01.0v2.0

Revision History:

04/04/2018Added v4.1 to Version Table (Xilinx Answer 70196) (Xilinx Answer 70581) and (Xilinx Answer 70591)
01/25/2018Added (Xilinx Answer 69274)
01/18/2018Added v4.0 (Rev. 1) to Version Table
11/03/2017Added (Xilinx Answer 69766) (Xilinx Answer 69671) (Xilinx Answer 69931) and (Xilinx Answer 69760)
10/23/2017Added v3.1 (Rev.1) and v4.0 to Version Table and (Xilinx Answer 67365)
06/05/2017Added (Xilinx Answer 69274)
04/05/2017Added v3.1 to Version Table, (Xilinx Answer 68803), (Xilinx Answer 68810) and (Xilinx Answer 69057)
02/07/2017Added v2.0 (Rev.1), v3.0 and v3.0 (Rev.1) to Version Table and (Xilinx Answer 68603)
05/31/2016Added (Xilinx Answer 67258), (Xilinx Answer 67296) and (Xilinx Answer 67249)
04/06/2016Added v2.0 to Version Table
12/07/2015Added (Xilinx Answer 66088)
09/30/2015Initial Release

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
66088 LogiCORE IP MIPI D-PHY Controller - Are there plans to support MIPI D-Phy v1.2? N/A N/A
67296 LogiCORE IP MIPI D-PHY Controller v2.0 - Are multi-lane use cases supported in MIPI D-PHY IP? N/A N/A
67249 LogiCORE IP MIPI D-PHY Controller - What is the maximum value of start-up time before High-speed data transfer? N/A N/A
67258 LogiCORE IP MIPI D-PHY Controller v2.0 - Why is there a change to the rxvalidhs behavior when receiving in high-speed mode? N/A N/A
68603 LogiCORE IP MIPI D-PHY Controller v3.0 (Rev. 1) – Slave Mode (Shared logic in example design) D-PHY RX IP does not work when it is sharing resources with Master mode (Shared Logic in core) D-PHY Receiver IP. N/A N/A
69057 LogiCORE IP MIPI D-PHY Controller v3.0 (Rev. 1) - Why is an SOTsynchs error generated from the MIPI DPHY RX IP or MIPI CSI-2 Rx Subsystem? N/A N/A
69173 2017.1 LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Patch Updates for the LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) N/A N/A
69250 LogiCORE IP MIPI CSI-2 Transmitter Subsystem v1.0 (Rev. 2) - Why is the MIPI Transmitter Clock/Data relationship not center-aligned for some line-rate configurations? N/A N/A
69274 LogiCORE IP MIPI D-PHY Controller v3.1, v3.1 (Rev. 1) and v4.0 (Rev. 1) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY Controller RX? N/A N/A
69530 LogiCORE MIPI D-PHY and MIPI CSI-2 RX Subsystem - How much margin is in the MIPI D-PHY RX line rate settings? N/A N/A
67365 LogiCORE IP MIPI D-PHY Controller v2.0 - What is the expected behavior of the receiver IP on the SoT pattern and why do I not see an error when sending "BC" and receiving "B8"? N/A N/A
69931 LogiCORE IP MIPI D-PHY Controller v3.1 (Rev. 1) - When using MIPI D-PHY TX, why is the HS-PREPARE length violating MIPI D-PHY specification version 1.1? N/A N/A
69766 LogiCORE IP MIPI D-PHY Controller v3.1 (Rev. 1) - When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes? N/A N/A
69671 LogiCORE IP MIPI D-PHY Controller v3.1 (Rev. 1) - When using 7 Series Devices to implement MIPI D-PHY TX, why do we see overshoot on the output signal during HS-->LP transmission? N/A N/A
69760 2017.2 LogiCORE IP MIPI D-PHY Controller v3.1 (Rev. 1) - Patch Updates for the MIPI D-PHY Controller LogiCORE IP v3.1 (Rev. 1) N/A N/A
70196 LogiCORE IP MIPI D-PHY v4.0 - On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRL N/A N/A
70581 LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) (or MIPI CSI-2 Receiver Subsystem v3.0 (Rev. 1)) - Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices? N/A N/A
70591 LogiCORE IP MIPI D-PHY v4.0 - Can I change IDELAY tap values on the fly for MIPI D-PHY IP v4.0? (IP targeting 7 Series devices) N/A N/A
70530 2017.4 LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) - Patch Updates for the MIPI D-PHY Controller LogiCORE IP v4.0 (rev.1) N/A N/A
69531 LogiCORE MIPI D-PHY v3.1, MIPI CSI-2 Rx Subsystem v2.2 (Rev. 1) - Why do I get warning "ncelab: *dphy_ip/mipi_dphy.srcs/sources_1/ip/mipi_dphy_rx1/mipi_dphy_rx1_core.v,436|49): implicit wire has no fanin" on system_rst_in when simulating the MIPI DPHY RX? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
65242 MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
67896 MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2016.3 tool and later versions N/A N/A
AR# 54550
Date 04/09/2018
Status Active
Type Release Notes
Devices
  • Zynq UltraScale+ MPSoC
  • Kintex UltraScale+
  • Virtex UltraScale+
IP
  • MIPI D-PHY

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