AR# 54643


7 Series Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions


This answer record contains the Release Notes and Known Issues for the 7 Series Integrated Block for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.

Please refer to XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


General Information

Supported Devices can be found in the following locations:

  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.


Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v3.3 (Rev12)2020.1
v3.3 (Rev11)2019.2
v3.3 (Rev11)2019.1
v3.3 (Rev10)2018.3
v3.3 (Rev9)2018.2
v3.3 (Rev8)2018.1
v3.3 (Rev7)2017.4
v3.3 (Rev6)2017.3
v3.3 (Rev5)2017.2
v3.3 (Rev4)2017.1
v3.3 (Rev3)2016.4
v3.3 (Rev2)2016.3
v3.3 (Rev1)2016.2
v3.0 (Rev4)2014.4
v3.0 (Rev3)2014.3
v3.0 (Rev2)2014.2
v3.0 (Rev1)2014.1


Design Advisory

(Xilinx Answer 62296)Design Advisory for 7 Series/Virtex-7 FGPA Gen3 Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2014.1/2014.2/2014.3) - Tool reports 'constant_clock' and 'unconstrained_internal_endpoints' when implementing core configured as Gen1
(Xilinx Answer 62770)Link training issue with GTP devices


Known and Resolved Issues

The following table provides known issues for the 7 Series Integrated Block for PCI Express core, starting with v2.0, initially released in Vivado Design Suite 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 72057)Gen2x4 Example Design Fails Timing with AC701v3.3 (Rev10)Not Resolved Yet
(Xilinx Answer 72010)Support for CPG236 Artix-7 package for x2 configurationv3.3 (Rev10)Not Resolved Yet
(Xilinx Answer 70553)user_reset_out (active-high) is connected to rst_n (active-low) input of pcie_7x_0_tandem_cpler module3.3 (Rev7)3.3 (Rev8)
(Xilinx Answer 63182)Link can intermittently fail to train on Artix-7 devices3.13.1(Rev1)
(Xilinx Answer 62854)Excessive BUFG usage3.0 (Rev 3)3.0 (Rev4)
(Xilinx Answer 61651)Secondary Bus Reset bit functionality in RP mode does not work as expected3.0 (Rev2)Not Resolved Yet
(Xilinx Answer 61652)ModelSim PE and DE Support3.0 (Rev2)Resolved in ModelSim PE and DE (10.3c)
(Xilinx Answer 60570)Example design Root Port model does not accept Non-Posted transactions3.0 (Rev2)3.0 (Rev3)
(Xilinx Answer 61402)PCIe x8Gen2 PIO example design for k70tfbg676-2 device fails in timing.3.0 (Rev2)v3.0 (Rev4)
(Xilinx Answer 61249)PIPE Simulation and External PIPE Interface options permanently disabled in RP mode3.0 (Rev2)v3.0 (Rev3)
(Xilinx Answer 59375)VCS/ModelSim simulation fails when simulating the core generated for Artix-7 device targeting VHDL3.0v3.0 (Rev3)
(Xilinx Answer 59900)Post Synthesis/Implementation Netlist Functional/Timing Simulation Support3.0 (Rev1)Not Resolved Yet
(Xilinx Answer 58738)Zynq 7015 (clg485 package) / Artix 35t (cpg236 and csg325 packages) and 50t devices support3.03.0 (Rev1)
(Xilinx Answer 58628)"CRITICAL WARNING/proj [Route 35-39] The design did not meet timing requirements..."3.03.0 (Rev1)
(Xilinx Answer 58604)External ports updated when upgrading the core from v2.0/v2.1 to v2.22.2NA
(Xilinx Answer 57823)Artix-7 SBG484 device support2.23.0
(Xilinx Answer 57764)TX de-emphasis setting is not set correctly on Lane 1 through Lane 7 in VHDL version of the core2.23.0
(Xilinx Answer 58052)Supported combinations of Target Language and Simulator Language2.2v3.0 (Rev2)
(Xilinx Answer 55529)CDC (Clock Domain Crossing) Issue2.02.1
(Xilinx Answer 55537)How to generate the core for production Zynq devices?2.02.1
(Xilinx Answer 55311)Downstream Memory Write transactions fail in VHDL example design simulation for the core generated with 128 bit interface width2.02.1
(Xilinx Answer 53250)Setup timing violation on userclk11.82.2
(Xilinx Answer 53550)128-bit user interface with 64-bit BAR simulation is not working - malformed packet sent by the Root Port Simulation Model (DSPORT)1.72.1
(Xilinx Answer 50683)MSI Per Vector Masking Capability Support1.7Not Resolved Yet
(Xilinx Answer 50692)The core might truncate some DLLPs/TLPs during the process of going into Recovery1.4Not Resolved Yet
(Xilinx Answer 50835)VHDL Simulation support for Root Port Configuration1.63.0
(Xilinx Answer 47626)VHDL Simulation Support in Endpoint Configuration1.42.2
(Xilinx Answer 47628)Timing Violations in Certain IP Configurations1.4Not Resolved Yet


Other Information:

(Xilinx Answer 62530)7 Series FPGAs Transceivers Wizard - PCIe GT Wrapper support in 2014.3 and later
(Xilinx Answer 67039)7 Series Integrated Block for PCI Express (Vivado 2014.3) - Link training issue with Gen2x1 designs
(Xilinx Answer 60606)Tandem PCIe second stage bitstream programming fails with larger BAR size
(Xilinx Answer 51950)Tandem PCIe Second Stage Bitstream Loading Across the PCI Express Link
(Xilinx Answer 52400)7 Series Integrated Block for PCI Express v1.9/2.0 - Asynchronous Clocking Support
(Xilinx Answer 53776)Generating Quick Test Cases for Xilinx Integrated PCI Express Block and Serial RAPIDIO Cores Verilog Simulation
(Xilinx Answer 53786)7 Series Integrated Block for PCI Express in Vivado
(Xilinx Answer 55084)7 Series Integrated Block Wrapper for PCI Express v2.0 - Verilog Instantiation Changed from Uppercase to Lowercase
(Xilinx Answer 56616)7 Series Integrated Block for PCI Express - Link Training Debug Guide
(Xilinx Answer 58495)Xilinx PCI Express Interrupt Debugging Guide
(Xilinx Answer 64605)7 Series Integrated Block for PCI Express - 31.25MHz AXI Interface Frequency Support
(Xilinx Answer 67006)Incorrect completion behavior with the example design when s_axis_tx_tready is deasserted


Revision History

02/25/2019Added (Xilinx Answer 72057)
02/11/2019Added (Xilinx Answer 72010)
04/19/2018Added (Xilinx Answer 70553)
04/16/2018Updated for 2018.1 Release
04/05/2017Updated for 2017.1 Release
01/24/2017Updated for 2016.4 Release
10/05/2016Updated for 2016.3 Release
08/06/2016Updated for 2016.2 Release
04/13/2016Updated for 2016.1 Release
11/24/2015Updated for 2015.4 Release
10/06/2015Updated for 2015.3 Release
06/24/2015Updated for 2015.2 Release
04/15/2015Updated for 2015.1 Release
11/24/2014Updated for 2014.4 Release
11/20/2014Added (Xilinx Answer 62530), (Xilinx Answer 62770) and (Xilinx Answer 62854)
11/09/2014Added (Xilinx Answer 62296)
10/08/2014Updated for 2014.3 Release
08/26/2014Added (Xilinx Answer 61651)
06/05/2014Added (Xilinx Answer 61652)
07/31/2014Added (Xilinx Answer 60570)
07/07/2014Added (Xilinx Answer 61402)
06/24/2014Added (Xilinx Answer 61249)
06/04/2014Updated for 2014.2 Release
05/28/2014Added (Xilinx Answer 60606)
04/16/2014Updated for 2014.1 Release
02/28/2014Added (Xilinx Answer 58738)
12/18/2013Updated for 2013.4 Release
10/23/2013Updated for 2013.3 Release
10/07/2013Added (Xilinx Answer 57764)
06/19/2013Updated for 2013.2 Release
06/13/2013Added (Xilinx Answer 55529)
05/02/2013Added (Xilinx Answer 55537)
04/03/013Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45382 Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Child Answer Records

AR# 54643
Date 07/23/2020
Status Active
Type Release Notes
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