KEEP
The KEEP attribute is used to prevent optimizations in which signals are optimized or absorbed into logic blocks. The attribute instructs the synthesis tool to keep the signal it was placed on, and that signal is placed in the netlist.
KEEP is commonly used in conjunction with timing constraints. If there is a timing constraint on a signal that would normally be optimized, KEEP will prevent this and allow the correct timing rules to be used.
In cases where other attributes are in conflict with KEEP, the KEEP attribute usually takes precedence over them:
Accepted values are:
Notes:
Verilog Example
(* keep = "true" *) wire sig1;
VHDL Example
signal sig1 : std_logic;
attribute keep : string;
attribute keep of sig1 : signal is "true";
Known Issues:
N/A
KEEP_HIERARCHY
The KEEP_HIERARCHY attribute is used to prevent optimizations along the hierarchy boundaries. The Vivado synthesis tool attempts to keep the same general hierarchies specified in the RTL, but it can flatten or modify them for QoR reasons.
If KEEP_HIERARCHY is placed on the instance, the synthesis tool keeps the boundary on that level static. This can affect QoR and also should not be used on modules that describe the control logic of 3-state outputs and I/O buffers.
The KEEP_HIERARCHY attribute can be placed in the module, architecture level, or the instance.
Accepted values are:
Verilog Example
On Module:
(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);
On Instance:
(* keep_hierarchy = "yes" *) bottom u0 (.in1(in1), .in2(in2), .out1(temp1));
VHDL Example
On Module:
attribute keep_hierarchy : string;
attribute keep_hierarchy of beh : architecture is "yes";
On Instance:
attribute keep_hierarchy : string;
attribute keep_hierarchy of u0 : label is "yes";
Known Issues:
N/A
RAM_STYLE
RAM style controls how the Vivado Synthesis tool infers memory. Accepted values are:
By default, the tool will select which RAM to infer based on heuristics that give the best results for the most designs. Place this attribute on the array that is declared for the RAM.
Verilog Example
(* ram_style = "distributed" *) reg [data_size-1:0] myram [2**addr_size-1:0];
VHDL Example
attribute ram_style : string;
attribute ram_style of myram : signal is "distributed";
Known Issues:
N/A
ROM_STYLE
ROM style controls how the Vivado Synthesis tool infers ROM memory. Accepted values are:
By default, the tool will select which ROM to infer based on heuristics that give the best results for the most designs.
Verilog Example
(* rom_style = "distributed" *) reg [data_size-1:0] myrom [2**addr_size-1:0];
VHDL Example
File Name | Attribute Example |
---|---|
keep.zip | KEEP |
keep_hierarchy.zip | KEEP_HIERARCHY |
ram_style.zip | RAM_STYLE |
rom_style.zip | ROM_STYLE |
Name | File Size | File Type |
---|---|---|
keep.zip | 1 KB | ZIP |
keep_hierarchy.zip | 1 KB | ZIP |
ram_style.zip | 1 KB | ZIP |
rom_style.zip | 1 KB | ZIP |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
55160 | Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support | N/A | N/A |
AR# 54778 | |
---|---|
Date | 06/04/2014 |
Status | Active |
Type | Solution Center |
Tools |