AR# 54845

MIG 7 Series v1.8 - No instantiation template provided for VHDL version of the core

Description

Version Found: v1.8
Version Resolved: See (Xilinx Answer 45195)

No VHDL instantiation template (.vho file) is provided with MIG. In the CORE Generator tool, when the design entry is set to VHDL, only a verilog instantiation template (.veo) is generated.

Solution

This is a known issue.

To work around this problem, use the instantiation in the example_top.vhd as a reference. The component declaration and instantiation for the user design can be copied directly from within example_top.vhd.

Revision History
04/03/2013 - Initial release

AR# 54845
Date 12/02/2013
Status Active
Type Known Issues
Devices More Less
IP