In Vivado 2013.1 tool, if you upgrade from a previous version of the Aurora 8B10B IP with a Verilog instantiation, the tools will issue an error message for each port. For example:
[Synth 8-448] named port connection 'S_AXI_TX_TDATA' does not exist for instance 'aurora_module_i' of module 'aurora_8b10b_v8_3_0' [aurora_8b10b_v8_3_0_exdes.v:285]
To drive consistency between Xilinx IPs, signal names in Verilog versions of the cores have been changed to use all lower case.
Therefore, the signal names in the IP instantiation are now in lower case.
For example, the "S_AXI_TX_TDATA" signal is now "s_axi_tx_tdata" in v9.0.
After the upgrade is completed, the instantiation in the design will need to be replaced with signal names in lower case..
4/22/2013 - Initial History