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AR# 55060

MIG 7 Series DDR3/DDR2, AXI Interface Enabled - Controller services write command before read is completed


This answer record applies to the MIG 7 series DDR3/DDR2 design with the AXI interface enabled.  When a long write or read burst is requested on the AXI interface and AXI is currently servicing a read request, there is chance for AXI to service the write request before read request is completed. After all write requests are served, AXI will send out the remaining read requests.


This is an AXI arbiter problem. The logic should not switch to write before read is completed. This generally does not impact the functionality, but for the design that requires strict write and read order, this may cause a functional problem. The workaround now is not to assert write and read at the same time. After the read is completed, the write should be then requested on AXI. There is no starvation timeout or wait timeout. This issue is planed to be fixed in 2013.
AR# 55060
Date 05/31/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2012.4
  • ISE Design Suite - 14.4
  • MIG 7 Series