AR# 55084


7 Series Integrated Block Wrapper for PCI Express v2.0 - Verilog Instantiation Changed from Uppercase to Lowercase


Version Found: Upgrading from v1.8 or earlier core to v2.0

In the Vivado 2013.1 tool, when upgrading from 7 Series Integrated Block Wrapper for PCI Express v1.8 core or earlier, errors similar to the following occur for a few of the core ports:

"ERROR: [Synth 8-448] named port connection 'PIPE_PCLK_IN' does not exist for instance 'pcie_7x_v1_8_0_i' of module 'pcie_7x_v1_8_0' [/.../design.srcs/sources_1/imports/pcie_7x_v1_8_0/example_design/xilinx_pcie_2_1_ep_7x.v:315]"


To drive consistency between Xilinx IPs, signal names in the Verilog cores have been changed to use all lowercase. Therefore, the higher level module where the core is instantiated should now have the following signals listed below in lowercase. Please upgrade the core first before changing the core instantiation in the design.


The * substitutes all character(s) following the specified prefix signal names.

In the example above, "PIPE_PCLK_IN" is now "pipe_pclk_in".

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AR# 55084
Date 11/06/2013
Status Active
Type Known Issues
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