If I synthesize the core within Vivado Design Suite 2013.1 with FIR Compiler v7.0, the block that implements a dynamic shift RAM is not being synthesized correctly.
This is a known issue with FIR Compiler v7.0. The error is confined to the following FIR Compiler configurations of the core:
The error will show up in any netlist simulation and in hardware as a persistent mismatch of M_AXIS_DATA_TDATA versus the desired behavior (as described by the simulation model).
To work around this issue, specify a second pattern where no channel appears in consecutive slots (e.g., 0101 or 01230123). This second pattern need not be used.