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AR# 55989

Vivado Synthesis - Why does a Xilinx IP not get flattened completely?


Vivado Synthesis does not flatten a Xilinx IP in spite of setting flatten_hierarchy to "full" or "rebuilt". For example, the design with IP (e.g., block memory and ethernet 100BASE-X PCS/PMA) cannot be flattened completely.

What is the reason for Vivado Synthesis not being able to completely flatten a Xilinx IP design?


The reason for Vivado Synthesis not flattening the Xilinx IP is that the tool generates a dont_touch.xdc file for all Xilinx IP instantiations; this file can be located beneath the synth directory. This file contains the following DONT_TOUCH property that causes the tool not to flatten the IP:

set_property DONT_TOUCH true [get_cells inst]

NOTE: This file should not be modified.

AR# 55989
Date 06/20/2013
Status Active
Type Known Issues
  • Vivado Design Suite