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AR# 56312

XAUI v10.4 rev1, v11.0 rev 1 - Update to 7 Series GTP/GTH reset logic

Description

The XAUI v10.4 rev1, v11.0 and v11.0 rev1 cores contain the GTP and GTH reset sequence required for production silicon. For more information on these requirements, see (Xilinx Answer 53779) and (Xilinx Answer 53561).  The GTRXRESET state machine expects the GTRXRESET in the DCLK domain while the block level wrapper issues this clock in the userclk (clk156) domain.  The below logic should be added to extend the GTRXRESET to ensure it correctly crosses to the dclk domain and also insure that a second reset is not issued while the previous reset is in progress.

Solution

To address this make the following changes to the <core_name>_block.v or vhd file:

VHDL

  signal mgt_rx_reset_stretched        : std_logic;
  signal mgt_rx_reset_inprocess        : std_logic := '0';
  signal mgt_rx_reset_stretched_unique : std_logic;
  signal mgt_rx_reset_stretch_r        : std_logic_vector(2 downto 0) := "000";

...
    GT0_GTRXRESET_IN                        => mgt_rx_reset_stretched_unique,
...
    GT1_GTRXRESET_IN                        => mgt_rx_reset_stretched_unique,
...
    GT2_GTRXRESET_IN                        => mgt_rx_reset_stretched_unique,
...
    GT3_GTRXRESET_IN                        => mgt_rx_reset_stretched_unique,
...

  process(pll_reset, reset, dclk)
  begin
    if pll_reset = '1' or reset = '1' then
      mgt_rx_reset_inprocess <= '0'; 
    elsif rising_edge(dclk) then
      if mgt_rx_reset_stretched = '1' then
        mgt_rx_reset_inprocess <= '1';
      end if;
      if (mgt_rxresetdone_reg = "1111") then
        mgt_rx_reset_inprocess <= '0';
      end if;
    end if;
  end process;

  process(dclk, mgt_rx_reset)
  begin
    if mgt_rx_reset = '1' then
      mgt_rx_reset_stretch_r(2) <= '1';
    elsif rising_edge(dclk) then
      mgt_rx_reset_stretch_r <= '0' & mgt_rx_reset_stretch_r(2 downto 1);
    end if;
  end process;

  mgt_rx_reset_stretched <= mgt_rx_reset_stretch_r(0);
  mgt_rx_reset_stretched_unique <= mgt_rx_reset_stretched and not mgt_rx_reset_inprocess;


Verilog

  wire       mgt_rx_reset_stretched;
  reg       mgt_rx_reset_inprocess = 1'b0;
  wire      mgt_rx_reset_stretched_unique;
  reg [2:0] mgt_rx_reset_stretch_r = 3'b000;

...
        .GT0_GTRXRESET_IN                   (mgt_rx_reset_stretched_unique),
...
        .GT1_GTRXRESET_IN                   (mgt_rx_reset_stretched_unique),
...
        .GT2_GTRXRESET_IN                   (mgt_rx_reset_stretched_unique),
...
        .GT3_GTRXRESET_IN                   (mgt_rx_reset_stretched_unique),
...

  always @(posedge pll_reset or posedge reset or posedge dclk)
  begin
    if (pll_reset || reset ) begin
      mgt_rx_reset_inprocess <= 1'b0;
    end
    else begin
      if (mgt_rx_reset_stretched) begin
       mgt_rx_reset_inprocess <= 1'b1;
      end
      if (mgt_rxresetdone_reg == 4'b1111) begin
        mgt_rx_reset_inprocess <= 1'b0;
      end
    end
  end

  always @(posedge dclk or posedge mgt_rx_reset)
  begin
    if (mgt_rx_reset) begin
      mgt_rx_reset_stretch_r[2] <= 1'b1;
    end
    else begin
      mgt_rx_reset_stretch_r <= {1'b0 , mgt_rx_reset_stretch_r[2 : 1]};
    end
  end

  assign mgt_rx_reset_stretched = mgt_rx_reset_stretch_r[0];
  assign mgt_rx_reset_stretched_unique = mgt_rx_reset_stretched && !mgt_rx_reset_inprocess;
AR# 56312
Date Created 06/10/2013
Last Updated 09/09/2013
Status Active
Type General Article
IP
  • XAUI