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AR# 56642

Zynq TRM v1.5 - Bit 24, 17, and 16 FPGA_RST_CTRL register descriptions are incorrect


On page 1542 of the Zynq SoC Technical Reference Manual v1.5 (UG585), it states that bits 24, 17, 16 in the slcr.FPGA_RST_CTRL register are 0x1, "Reserved. Do not modify." All other bits, except for bits 3..0, can or must be written as 0.

Is this correct?


No, this is not correct. Bits 24, 17, 16 register descriptions are incorrect.

Instead of:

Bits 24, 17, 16;

  Reserved. Do not modify.

This should be read as:

Bits 24, 17, 16

  Reserved - always write with 0

These are the ACP, and GP resets, and must be written to 0 to work.

AR# 56642
Date 05/17/2018
Status Active
Type General Article
  • Zynq-7000
  • EDK - 14.6
  • Vivado Design Suite - 2013.2
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