On page 1542 of the Zynq SoC Technical Reference Manual v1.5 (UG585), it states that bits 24, 17, 16 in the slcr.FPGA_RST_CTRL register are 0x1, "Reserved. Do not modify." All other bits, except for bits 3..0, can or must be written as 0.
Is this correct?
No, this is not correct. Bits 24, 17, 16 register descriptions are incorrect.
Bits 24, 17, 16;
Reserved. Do not modify.
This should be read as:
Bits 24, 17, 16
Reserved - always write with 0
These are the ACP, and GP resets, and must be written to 0 to work.