The following error was seen during MAP for an incorrect IODELAY configuration involving VAR_LOADABLE mode:
Please refer to the Virtex-6 FPGA SelectIO Resources User Guide (UG361), under the section "IODELAYE1 Ports".
"Clock Input - C
All control inputs to IODELAYE1 primitive (RST, CE, and INC) are synchronous to the clock input (C).
A clock must be connected to this port when IODELAYE1 is configured in VARIABLE or VAR_LOADABLE mode.
C can be locally inverted, and must be supplied by a global or regional clock buffer.
This clock should be connected to the same clock in the SelectIO logic resources (when using ISERDES and OSERDES, C is connected to CLKDIV)."
The C pin should be connected to the same clock as the ISERDES's CLKDIV.