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AR# 57358

AXI 10G Ethernet Subsystem - Release Notes and Known Issues for Vivado 2013.3 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the AXI 10-Gigabit Ethernet core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

The AXI 10-Gigabit Ethernet Core uses the 10-Gigabit Ethernet MAC core and 10-Gigabit Ethernet PCS/PMA core. 

For the Release Notes and Known issues for these cores, please refer to:

(Xilinx Answer 54252) - 10-Gigabit Ethernet MAC Core Release Notes and Known Issues
(Xilinx Answer 54669) - 10-Gigabit Ethernet PCS/PMA Core Release Notes and Known Issues

AXI 10-Gigabit Ethernet Core IP Pages:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi_10g_ethernet.html

Solution

General Information

Supported devices can be found in the following locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core
Version
Vivado Tool
Version
v3.0 2015.1
v2.0 (Rev. 2)
2014.4.1
v2.0 (Rev. 1) 2014.4
v2.0 2014.3
v1.2 (Rev. 1) 2014.2
v1.2 2014.1
v1.1 2013.4
v1.0 2013.3


General Guidance

The table below provides answer records for general guidance when using the AXI 10-Gigabit Ethernet core.

Answer Record Title
(Xilinx Answer 38279) Ethernet IP Solution Center


Known and Resolved Issues

The following table provides known issues for the AXI 10-Gigabit Ethernet core.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version
Found
Version
Resolved
NA 7 Series - Updates needed to reset logic if using 1588
v2.0 v3.0
(Xilinx Answer 63106) AXI lite interface failures seen when using 64-bit master v2.0 v3.0
(Xilinx Answer 63415) 1588 - early rollover of timestamp seconds field v2.0 v2.0 Rev. 2
(Xilinx Answer 62299) MDIO port address change NA v2.0
(Xilinx Answer 60085) Incorrect register address documented for RX Fixed Latency v1.0 See AR
(Xilinx Answer 58831) Issue seen with timestamping and UDP checksum
v1.1 v1.2
(Xilinx Answer 58257) IP should be marked Pre-production status in 2013.3 v1.0 NA


Revision History

10/23/2013 - Initial release

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 57358
Date Created 09/04/2013
Last Updated 04/30/2015
Status Active
Type Release Notes
IP
  • AXI 10 Gigabit Ethernet