AR# 57561

Example Design - Using the AXI DMA in polled mode to transfer data to memory

Attached to this Answer Record is an Example Design for using the AXI DMA in polled mode to transfer data to memory.

This design targets Zynq devices and uses a simple counter to drive the S2MM channel of the AXI DMA.

Counter data is sent into and then read out of memory, and is finally sent out of the MM2S channel to an AXI Streaming FIFO.

The data received by the AXI Streaming FIFO is verified against the counter data.

The ARM controls DMA transfers via GP ports by accessing the AXI DMA core through its AXI Lite interface.

It uses simple polling of the status register to manage DMA transfers.

For more details about the design, refer to the dma_ex_polled/doc directory.

The current version of this design was created in Vivado 2015.1.

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Name	File Size	File Type
dma_ex_polled_v2_1.zip	1 MB	ZIP
simple_dma.xpr.zip	32 MB	ZIP

Answer Number	Answer Title	Version Found	Version Resolved
57550	Example Designs - Designing with the AXI DMA core	N/A	N/A

AR# 57561
Date	05/18/2018
Status	Active
Type	General Article
Devices	Zynq-7000
Tools	Vivado Design Suite - 2013.2
IP	AXI DMA Controller AXI DMA Controller AXI Streaming FIFO AXI Interconnect AXI Interconnect More Less
Boards & Kits	Zynq-7000 SoC Boards and Kits