If simulated using IES or XSIM, the output of the DFT core (netlist) may differ from hardware in terms of bit-accuracy of the data values versus the C model or simulation model.
This is known issue with Discrete Fourier Transform (DFT) core simulation with IES or XSIM.
The error will be an infrequent difference of the order of 1ulp, rather than a catastrophic error, as it is due to a rounding error of a single twiddle factor.
Frequency of error is low, however it can occur with any core configuration
The suggested work-around is to simulate using QUESTA/MTI.
You can tolerate these small numerical differences from the expected output depending on the application.