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AR# 5865

Virtex-II/-II Pro/-4/-5/-6 Configuration - The DONE pin goes High, but the device does not start up (I/Os are inactive/3-stated)


I am configuring a Xilinx Virtex series FPGA at high speed. The DONE pin goes High, but the device does not start up; the I/Os are still put into a 3-state condition.


There are a handful of problems that might prevent a Xilinx Virtex series FPGA from operating correctly after the DONE pin goes High:

1. A slow rise time on the DONE pin

2. An incorrect startup clock

3. Insufficient clock cycles to complete the startup sequence

4. Contention between DONE signals on configured vs. unconfigured devices

1. A slow rise time on the DONE pin

The DONE pin must transition from Low to High within one CCLK cycle. For example, if CCLK is running at 33 MHz in slave serial mode, the rise time of the DONE pin must be less than 25 ns. The DONE pin is an open-drain driver by default, and it must be pulled High externally.

If DONE can not transition from Low to High within one CCLK cycle, the Startup sequence may not complete properly, and thereby configuration may fail. This applies to all Xilinx FPGAs.

Potential Remedies:

a) Attach an external pull-up resistor to the DONE signal (the recommended value is 330 Ohms).

b) In BitGen, set "DonePipe=Yes" to delay the CFG_DONE signal. This setting adds a pipelined register stage to the DONE input (CFG_DONE) path.

c) Alternatively, set the BitGen "DriveDone=Yes" option to actively drive the DONE pin. (NOTE: This option should only be used if you are configuring one device or the device is last in a daisy chain.)

2. An incorrect startup clock is selected

For Virtex and Virtex-II devices, you must select the clock to use for the startup sequence: either CCLK, JTAG Clock (TCK) or a user-defined clock. If an incorrect startup clock is used, the device may configure, but it will not complete the startup sequence. Check the BitGen options in the bitgen.ut file to ensure that the correct startup clock is used.

3. Insufficient startup clock cycles to complete startup sequence

The device may not start up if it is not receiving enough CCLK cycles to take it through the startup sequence. This problem is especially prevalent in configuration setups in which the DONE pins are not tied together.

Potential Remedies:

a) If possible, connect the DONE pins in a serial daisy chain.

b) Give the device more CCLK cycles.

c) Change the BitGen options to set the DONE pin to go High last. (Please note that the second option can cause negative effects on daisy chain configurations.)

4. Contention between DONE signals on configured vs. unconfigured devices.

In a serial daisy chain, the DONE pin on upstream devices (closest to the configuration source) will be released before the downstream devices are configured. Unconfigured devices will actively drive the DONE signal Low.

If the BitGen "DriveDone=Yes" option is set for upstream devices, contention will occur on the DONE signal: an upstream device will be driving the DONE signal High while downstream devices are driving the DONE signal Low. To correct this problem, set "DriveDone=No" for all devices except for the last in a serial daisy chain.

If the STARTUP component is used in the design, the GSR pin might be getting asserted. This would prevent all flip-flops in the FPGA from transitioning.

The STARTUP component has a GSR input pin that is ACTIVE-HIGH. If this is being used, check the following:

- The driving source

- The state of the driving source

- Whether the GSR line has been inverted or needs to be inverted

AR# 5865
Date 02/04/2013
Status Active
Type General Article