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AR# 58855

MIG 7 Series DDR3/DDR2 - The AXI address width is incorrect if MIG is generated in an IPI block diagram

Description

Version Found: MIG 7 Series v2.0
Version Resolved: Vivado 2013.4 - See (Xilinx Answer 54025)

When adding a MIG 7 Series block to an IPI project that is configured with a UI Data Width of 64, Memory Interface Data width of 16, PHY to MC Clock ratio of 4:1, Bank width of 3, Row width of 15, and Column width of 10, the AXI Address Width should be 31 but is instead set to 29. The option is greyed out and unselectable.  How do you work around this issue?

This issue only affects MIG IPI flow in Vivado Design Suite 2013.3.

Solution

If moving to Vivado Design Suite 2013.4 is not feasible, use the following steps to work around the issue:

  1. Add an MIG IP in IPI block diagram.
  2. Generate it with wrong AXI Address Width.
  3. Open mig.prj, set C0_MEM_SIZE to 2147483648 (was 536870912) , set C0_S_AXI_ADDR_WIDTH to 31 (was 29).
  4. Regenerate MIG in IPI block diagram, it will generate the files with proper settings.


Revision History
12/20/2013 - Initial release

AR# 58855
Date Created 12/17/2013
Last Updated 01/02/2014
Status Active
Type General Article
Devices
  • Zynq-7000
IP
  • MIG 7 Series