Version Found: MIG 7 Series v2.0
Version Resolved: Vivado 2013.4 - See (Xilinx Answer 54025)
When adding a MIG 7 Series block to an IPI project that is configured with a UI Data Width of 64, Memory Interface Data width of 16, PHY to MC Clock ratio of 4:1, Bank width of 3, Row width of 15, and Column width of 10, the AXI Address Width should be 31 but is instead set to 29. The option is greyed out and unselectable. How do you work around this issue?
This issue only affects MIG IPI flow in Vivado Design Suite 2013.3.
If moving to Vivado Design Suite 2013.4 is not feasible, use the following steps to work around the issue:
12/20/2013 - Initial release