MIG 7 Series includes specific trace matching requirements between CK/Addr, DQ/DQS and CK/DQS.
The matching requirements are dependent on the target data rate, FPGA, and memory device and must include both PCB trace delay and package delay.
To view the matching requirements (including derating values), please refer to the DDR3 Design Guidelines section within (UG586).
This answer record includes an automated checker to help with understanding the requirements for your specific system or for verifying previously laid out boards.
Please use the attached 7Series_DDR3_PCB_Checker.xlsm and follow the steps below to generate the trace matching requirements.
How to use this tool: