The 7 Series FPGA GTX/GTH Transceivers User Guide v1.9.1 (UG476) or earlier revisions indicate that both CPLL and QPLL can be used for PCI Express Gen1 and Gen2 rates.
However, the PCIe Gen1 and Gen2 solution was only tested and validated using the CPLL.
Using QPLL in PCIe Gen1 and Gen2 mode is not supported.
The 7 Series FPGA GTX/GTH Transceivers User Guide is updated in the next revision v1.10 to reflect this.
Note: The above recommendation does not affect Xilinx 7 series Integrated Block for PCI Express core as it supports CPLL only.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 42944 | Design Advisory Master Answer Record for Virtex-7 FPGA | N/A | N/A |
| 42946 | Design Advisory Master Answer Record for Kintex-7 FPGA | N/A | N/A |
| AR# 59035 | |
|---|---|
| Date | 09/12/2014 |
| Status | Active |
| Type | Design Advisory |
| Devices |
|