Properties written in VHDL file in are silently ignored if the string value does not match the case (typically UPPER CASE) of the allowed property values.
Example: If a string-type property with an allowed value set of STOP and GO, setting the property to Stop, "stop", Go, or go will result in having the property ignored or disable because it does not have a valid value.
Using the command "write_xdc -sdc" after opening the Implemented design, I could see a list of "set_disable_timing" constraints applied to some components pins and cells.
However, I would expect the property values to be recognized if they only vary by case format. Otherwise, I would expect to see a warning indicating that the property is going to be ignored.
Property values should be written with the case outlined in the user guides. In most cases, this will be an all upper case format. Convert the value to upper case, but that we match the case of allowed values before storing.
However, Vivado should accept property values that vary only by case or give a good message indicating that the property is ignored.
This issue is fixed in Vivado Design Suite 2014.1.
A patch for this issue is available for Vivado Design Suite 2013.4.
With the patch and in Vivado 2014.1, the string values will be converted to match the case of allowed values before storing.
The patch for Vivado Design Suite 2013.4 is attached to this answer record.