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AR# 59173

14.7 ISE Place - New DRC check in ISE 14.7 catches faulty BUFR placement that previously went undetected


A new DRC check was added to ISE 14.7 to catch cases where a BUFR was not automatically placed in the same clock region as the CCIO (clock capable IO pin) that was driving it.

ERROR:PhysDesignRules:2506 - Incorrect placement for a BUFR component. BUFR DDR3_SDRAM/DDR3_SDRAM/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync in clock region CLOCKREGION_X1Y3 is driven by a CCIO CLK_P in clock region CLOCKREGION_X1Y2. The BUFR should be placed in the same clock region as the CCIO or the CLOCK_DEDICATED_ROUTE constraint should be used on the net <DDR3_SDRAM/DDR3_SDRAM/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/rsync_odelay<0>>.


This problem can be resolved by constraining the BUFR to the same clock region as the CCIO pin:


Note: The message's recommendation to place a CLOCK_DEDICATED_ROUTE on the clock net does not work. The proper way to bypass the error is to apply a CLOCK_DEDICATED_ROUTE = FALSE constraint to the output pin of the IBUDGDS driving the BUFR. Fixing the BUFR placement would normally be the preferred solution.

AR# 59173
Date 01/21/2014
Status Active
Type General Article
  • Virtex-6
  • ISE Design Suite - 14.7