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AR# 59317

Vivado IP Flows - How can I determine what constraints from my IP core are being applied to the top design?


When a design with an IP core is synthesized or implemented, constraints from the IP core are applied to the top level design. The constraints from the core are "scoped" to the top level in order to match the correct hierarchy.

Is there any way to check what the scoped constraints of an IP end up as? The temporary xdc file seems to be wiped out at the end of a run.

I am seeing a warning indicating that an IP constraint does not match any objects. However, the object in the constraint appears to be correct. I would like to see what scoped constraint was applied to the design. Is there a way to do this?


There is no way to report the completely scoped constraints per se, however, the following ideas may be of use:

  • You can run write_xdc after synthesis or implementation. This will report the scoped constraints but, not the fully resolved hierarchy.
  • You can add a synthesis option of -debug and it will produce an XDC which has all the constraints that are passed to synthesis. There will now be a debug.xdc that is put in the run directory for the IP if you do it for the IP run, or for the top level run if you do it for the whole design. This will show scoping information which sets the scope level to that of the IP and then the constraints which will be applied.
  • To get all of the applied constraint files use the following command.
  • get_files -compile_order constraints -used_in synthesis

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AR# 59317
Date 02/04/2014
Status Active
Type General Article
  • Vivado Design Suite
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