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AR# 60166

MIG 7 Series LPDDR2 - [Route 35-54] Net: is not completely routed


Version Found: MIG 7 Series v2.0 Rev 2
Version Resolved: See (Xilinx Answer 54025)

There is a known issue with MIG 7 Series LPDDR2 designs where the PHY_#_BITLANES parameter can be set incorrectly.

This can cause the design to fail during implementation with the following error message:
[Route 35-54] Net: example_top_inst/u_de_lpddr2_b4/u_de_lpddr2_b4_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clk is not completely routed.

The MIG design has top-level pin out parameters that are specifically assigned values to match the pin out.
If any of the pin out in the XDC has been modified the MIG core must be regenerated so that the rest of the parameters and design files get updated accordingly.
Otherwise, unrouted nets can also occur.


If the pin out and top-level pin out parameters have not been modified then verify the PHY_#_BITLANES parameters are set correctly.

UG586 v2.0 Table 4-27 contains the parameter definition and examples and should be used as a reference for validating your parameter setting.

Revision History
04/16/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60166
Date 04/15/2014
Status Active
Type Known Issues
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