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AR# 60480

MIG 7 Series - Receiving ERROR: [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but the backbone resources are not used

Description

Version Found: MIG 7 Series v2.0 Rev 2
Version Resolved: See (Xilinx Answer 54025)

For designs that previously generated a bit file successfully in 2013.4, you may now receive the following error related to the BACKBONE routing even though the CLOCK_DEDICATED_ROUTE constraint is applied correctly:

ERROR: [Drc 23-20] Rule violation (RTRES-1) Backbone resources - 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are clk_in1.


Solution

This issue can occur for some designs where SYS_CLK is not within the same bank as the MIG interface.

For example, 2 MIG interfaces sharing one SYS_CLK or 1 MIG interface where the SYS_CLK is in a different bank.

A conflict can occur when, the design is routing which, causes the net assigned to the backbone, not to be able to get onto the backbone routing and as such the DRC received is correct. 

However, this is still an issue as the tools should be able to handle this configuration.

Note: The routing was incorrect in previous SW versions as well, the DRC is new in 2014.1. 

This workaround would also be required with release 2013.4 and prior.

To check whether your net has been correctly placed on the backbone in previous SW versions where the DRC is not flagged, customers can run the following command on an open implemented design.

get_property route [get_nets clk_in1]
{ IOB_IBUF0 LIOI_I0 LIOI_ILOGIC0_D IOI_ILOGIC0_O IOI_LOGIC_OUTS18_1 INT_INTERFACE_LOGIC_OUTS_L18 WW2BEG0 NR1BEG0 LV18 LV18 { LV18 LV18 LV18 LV18 SW6BEG0 ER1BEG1 CLK0 CMT_R_LOWER_B_CLK_IN1_INT CMT_LR_LOWER_B_MMCM_CLKIN1 }  SW6BEG0 ER1BEG1 CLK1 CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT CMT_TOP_R_UPPER_T_PLLE2_CLKIN1 } 

It is clear that no Backbone has been used as in the route properties you should see "BB" used, see the below workaround for an example of a working route.

There is a workaround available for this issue, which is to directly apply a routing property to the net requiring the backbone routing.

The steps below show how this can be achieved:

  1. Open the implemented design and from the Tcl console perform the following:
    • report_drc -file pre_wa_drc_chk.rpt
      This performs a DRC check and shows the DRC reported by write_bitstream.
    • route_design -unroute
      Unroutes the entire design.
    • route_design -nets [get_nets clk_in1]
      Routes the net reported in the DRC error only.
    • set_property IS_ROUTE_FIXED 1 [get_nets clk_in1]
      Locks the net.
    • route_design
      Routes the rest of the design.
    • report_drc -file post_wa_drc_chk.rpt
      DRC error no longer reported.
  2. Now you will need to create a route constraint to add to the XDC file to ensure that the tools will successfully route the design and that this clk net will be placed on the backbone routing as required.

    get_property route [get_nets clk_in1]
    { IOB_IBUF0 LIOI_I0 LIOI_ILOGIC0_D IOI_ILOGIC0_O LIOI_I2GCLK_TOP0 HCLK_CMT_MUX_OUT_FREQ_REF0 HCLK_CMT_FREQ_REF_NS0 MMCM_CLK_FREQ_BB_REBUF0_NS PLL_CLK_FREQ_BB0_NS { CMT_TOP_R_UPPER_T_FREQ_BB0 CMT_TOP_R_UPPER_T_PLLE2_CLKIN1 } MMCM_CLK_FREQ_BB_REBUF0_NS PLL_CLK_FREQ_BB0_NS CMT_R_LOWER_B_CLK_FREQ_BB3 CMT_LR_LOWER_B_MMCM_CLKIN1 }

    This shows the connections for the clk_in1 net. You can see the Backbone is used, and see BB referenced in names.

  3. To make this workaround push button in the flow, you need to add an XDC constraint as follows:

  4. set_property route 
    { IOB_IBUF0 LIOI_I0 LIOI_ILOGIC0_D IOI_ILOGIC0_O LIOI_I2GCLK_TOP0 HCLK_CMT_MUX_OUT_FREQ_REF0 HCLK_CMT_FREQ_REF_NS0 MMCM_CLK_FREQ_BB_REBUF0_NS PLL_CLK_FREQ_BB0_NS  { MMCM_CLK_FREQ_BB_REBUF0_NS PLL_CLK_FREQ_BB0_NS CMT_R_LOWER_B_CLK_FREQ_BB3 CMT_LR_LOWER_B_MMCM_CLKIN1 }  CMT_TOP_R_UPPER_T_FREQ_BB0 CMT_TOP_R_UPPER_T_PLLE2_CLKIN1 } [get_nets clk_in1]


With this added, the design will implement and allow bitstream generation.

This AR also applies to 2013.4 designs.

Revision History

05/07/2014 - Initial Release


AR# 60480
Date Created 05/01/2014
Last Updated 06/19/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.1
IP
  • MIG 7 Series