UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61155

7-Series GTH Wizard v3.2 - GT Wizard generates wrong attributes

Description

When I use the Vivado 2013.4 or 2014.1 GTH Wizard, it generates incorrect GT attributes.
 
The example design can pass functional simulation but it fails to work on board.

I have selected "SRIO Gen2 Multiple lanes", 6.25Gbps, 156.25MHz REFCLK TX/RX QPLL

Solution

The generated attribute "QPLL_FBDIV_TOP" (QPLL_FBDIV_IN) is wrong.

However if you select "Start from scratch" and the same settings, the attribute is correct.

The incorrect value is 40, the correct value should be 80.

The problem cannot be seen in simulation.
 
Both 40 and 80 can work here.
 
QPLL_FBDIV_IN=40, RXOUT_DIV=1
QPLL_FBDIV_IN=80, RXOUT_DIV=2
 
However, GTH QPLL VCO should be larger than 8G.
 
As a result QPLL_FBDIV_IN=40 is wrong.
 
This will be fixed in the next version of the wizard.
AR# 61155
Date Created 06/16/2014
Last Updated 06/24/2014
Status Active
Type General Article
Devices
  • Virtex-7
IP
  • 7 Series FPGAs Transceivers Wizard