I am receiving the Fatal error below when simulating the core to try to read registers with an address >= 0x318:
This error is received in simulations with HD and PFC register access when these options are not enabled.
This particular address, 0x318, points to the Statistics Counter for TX Multiple Collision Frames.
This Statistics counter is only defined in the RTL when HD support is enabled at the time of generating the IP.
As a result, theoretically it should not be addressed when there is no HD support in the IP.
The read address decoder in the RTL does not validate the address on bus and as a result the out of range errors are received in simulation.
This issue has been fixed in Vivado 2016.1.
Any registers or counters that are optionally included based on characterization should cleanly return 0s when not configured into the core.
This will greatly simplify driver code and end-user use of the block.