Version Found: v2.3 (Rev1)
Version Resolved and other known issues: (Xilinx Answer 54646)
When generating the AXI Bridge for a PCI Express v2.3 (Rev1) core, the tool allows the core to be generated for x8 Gen2.
However, the core only supports up to x4 link width at Gen2 speed.
x8 link width is supported only for Gen1 speed.