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AR# 61652

7-Series FPGA Integrated Block Wrapper for PCI Express v3.0 (Rev2) - Example design simulation fails with Modelsim PE and DE


When simulating the 7 Series FPGA Integrated Block Wrapper for PCI Express v3.0 (Rev2) core example design in Modelsim PE and DE (10.2), the following error message is received:

# TIMEOUT ERROR in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.


This is a known issue with version 10.2 of Modelsim PE and DE. 

It has been fixed in 10.3c.

Modelsim SE, Questasim and Vivado Simulator do not have this issue.

Revision History

08/06/2014 - Initial Release

AR# 61652
Date 08/12/2014
Status Active
Type General Article
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