AR# 61898

AXI Bridge for PCI Express Gen3 - Release Notes and Known Issues for Vivado 2014.3 and newer tool versions

This answer record contains the Release Notes and Known Issues for the AXI Bridge for PCI Express Gen3 Core and includes the following:

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.3 and newer tool versions.

This article is part of the PCI Express Solution Centre

Xilinx Solution Center for PCI Express

Supported devices can be found in the following three locations:

Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
AXI Bridge for PCI Express Gen3 Product Guide (PG194)

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Tactical Patch

The following table provides a list of tactical patches for the AXI Bridge for PCI Express Gen3 applicable to corresponding Vivado tool versions.

Answer Record	Core Version (After installing the Patch)	Tool Version	Issues Fixed
(Xilinx Answer 63113)	v1.0 (Rev. 2)	2014.4	(Xilinx Answer 63113)
(Xilinx Answer 65744)	v2.0 (Rev. 65744)	2015.3	(Xilinx Answer 65744)
(Xilinx Answer 65831)	v2.0 (Rev. 65831)	2015.3	(Xilinx Answer 65744) (Xilinx Answer 65831)
(Xilinx Answer 67440)	v2.1 (Rev. 67440)	2016.1	(Xilinx Answer 67440)
(Xilinx Answer 69459)	v3.0 (Rev 69459)	2017.1/2017.2	(Xilinx Answer 69459)

Known and Resolved Issues

The following table provides known issues for the AXI Bridge for PCI Express Gen3 core, starting with v1.0, initially released in Vivado 2014.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record	Title	Version Found	Version Resolved
(Xilinx Answer 69459)	Critical Warning - [filemgmt 20-1741] File 'axi_pcie3_v1_1_bram_wrap.v' is used by one or more modules, but with different contents, and may lead to unpredictable result	v3.0 (Rev2) / v3.0 (Rev3)	v3.0 (Rev4)
(Xilinx Answer 67422)	Link up failure after multiple resets	v2.1(Rev1)	v3.0
(Xilinx Answer 67440)	[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_pcie3_0'	v2.1	v2.1 (Rev1)
(Xilinx Answer 65569)	Virtex-7 GTH QPLL temperature compensation attribute update		v2.1 (Rev1)
(Xilinx Answer 67172)	Example Design Simulation with VCS Simulator hangs indefinitely	v2.1	Not Resolved Yet
(Xilinx Answer 65831)	GT DRP Ports disabled when Falling Edge Receiver Detect is selected	v2.0	v2.0 (Rev1)
(Xilinx Answer 65744)	Enabling both MSI and MSI-X in the same design	v2.0	v2.0 (Rev1)
(Xilinx Answer 65500)	Example Design Simulation with VCS Simulator Fails	v2.0	v2.0 (Rev1)
(Xilinx Answer 65462)	Link Up Bit (Bit[11]) in Phy Status Register is Not Asserted	v2.0	v2.0 (Rev1)
(Xilinx Answer 64829)	AXI Master/Slave Outstanding Read/Write Transactions Limitation	v1.1(Rev1)	v2.0
(Xilinx Answer 63113)	Memory Read may not work in specific conditions	v1.0(Rev1)	v1.0(Rev2)
(Xilinx Answer 62515)	VC709 example design fails during implementation	v1.0	v1.0(Rev1)
(Xilinx Answer 62065)	Questa Simulation fails with SIGABRT error	v1.0	Fixed in QuestaSim 10.3c_1

Other Information:

(Xilinx Answer 63077)	s_axis_arready is not asserted by default
(Xilinx Answer 65074)	TSK_TX_MEMORY_WRITE_32 uses the incorrect value of tkeep

Revision History:

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