AR# 61898


AXI Bridge for PCI Express Gen3 - Release Notes and Known Issues for Vivado 2014.3 and newer tool versions


This answer record contains the Release Notes and Known Issues for the AXI Bridge for PCI Express Gen3 Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.3 and newer tool versions.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
  • AXI Bridge for PCI Express Gen3 Product Guide (PG194)
Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v3.0 (Rev 8)2018.3
v3.0 (Rev 7)2018.2
v3.0 (Rev 6)2018.1
v3.0 (Rev 5)2017.4
v3.0 (Rev 4)2017.3
v3.0 (Rev 3)2017.2
v3.0 (Rev2)2017.1
v3.0 (Rev1)2016.4
v2.1 (Rev1)2016.2
v2.0 (Rev1)2015.4
v1.1 (Rev1)2015.2.1
v1.1 (Rev1)2015.2
v1.0 (Rev2)2014.4
v1.0 (Rev1)2014.4


Tactical Patch

The following table provides a list of tactical patches for the AXI Bridge for PCI Express Gen3 applicable to corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool VersionIssues Fixed
(Xilinx Answer 63113)v1.0 (Rev. 2)2014.4(Xilinx Answer 63113)
(Xilinx Answer 65744)v2.0 (Rev. 65744)2015.3(Xilinx Answer 65744)
(Xilinx Answer 65831)v2.0 (Rev. 65831)2015.3(Xilinx Answer 65744)
(Xilinx Answer 65831)
(Xilinx Answer 67440)v2.1 (Rev. 67440)2016.1(Xilinx Answer 67440)
(Xilinx Answer 69459)v3.0 (Rev 69459)2017.1/2017.2(Xilinx Answer 69459)


Known and Resolved Issues

The following table provides known issues for the AXI Bridge for PCI Express Gen3 core, starting with v1.0, initially released in Vivado 2014.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69459)Critical Warning - [filemgmt 20-1741] File 'axi_pcie3_v1_1_bram_wrap.v' is used by one or more modules, but with different content, and can lead to unpredictable resultsv3.0 (Rev2) / v3.0 (Rev3)v3.0 (Rev4)
(Xilinx Answer 67422)Link up failure after multiple resetsv2.1(Rev1)v3.0
(Xilinx Answer 67440)[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'axi_pcie3_0'v2.1v2.1 (Rev1)
(Xilinx Answer 65569)Virtex-7 GTH QPLL temperature compensation attribute update v2.1 (Rev1)
(Xilinx Answer 67172)Example Design Simulation with VCS Simulator hangs indefinitelyv2.1Not Resolved Yet
(Xilinx Answer 65831)GT DRP Ports disabled when Falling Edge Receiver Detect is selectedv2.0v2.0 (Rev1)
(Xilinx Answer 65744)Enabling both MSI and MSI-X in the same designv2.0v2.0 (Rev1)
(Xilinx Answer 65500)Example Design Simulation with VCS Simulator Failsv2.0v2.0 (Rev1)
(Xilinx Answer 65462)Link Up Bit (Bit[11]) in Phy Status Register is Not Assertedv2.0v2.0 (Rev1)
(Xilinx Answer 64829)AXI Master/Slave Outstanding Read/Write Transactions Limitationv1.1(Rev1)v2.0
(Xilinx Answer 63113)Memory Read may not work in specific conditionsv1.0(Rev1)v1.0(Rev2)
(Xilinx Answer 62515)VC709 example design fails during implementationv1.0v1.0(Rev1)
(Xilinx Answer 62065)Questa Simulation fails with SIGABRT errorv1.0Fixed in QuestaSim 10.3c_1


Other Information:

(Xilinx Answer 63077)s_axis_arready is not asserted by default
(Xilinx Answer 65074)TSK_TX_MEMORY_WRITE_32 uses the incorrect value of tkeep
(Xilinx Answer 71427)ERROR: [DRC REQP-1910] PCIE31_invalid_MCAPPERSTxB_driver
(Xilinx Answer 71322)Reading AXI PCIe Gen3/XDMA internal registers using JTAG to AXI Master IP
(Xilinx Answer 73172)Baremetal design picks generic driver in SDK

Xilinx Forums:

Please seek technical support via the PCI Express board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Revision History:

10/02/2014Initial release
11/24/2014Updated for 2014.4 Release
12/17/2014Added (Xilinx Answer 63077)
01/07/2015Added (Xilinx Answer 63113)
04/15/2015Updated for 2015.1 Release
06/24/2015Updated for 2015.2 Release
10/06/2015Updated for 2015.3 Release
11/24/2015Updated for 2015.4 Release
04/13/2016Updated for 2016.1 Release
05/12/2016Added (Xilinx Answer 67172)
09/08/2016Updated for 2016.2 Release
07/05/2016Added (Xilinx Answer 65569)
08/19/2016Added (Xilinx Answer 67422)
10/05/2016Updated for 2016.3 Release
07/18/2017Added (Xilinx Answer 69459)
AR# 61898
Date 08/27/2020
Status Active
Type Release Notes
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