Does Vivado Synthesis make use of the parity bits for Asymmetric block RAM inference?
For example, when the write port is 9x4K and the read port is 36x1K, it fits into a single block RAM if the parity bits are used for the read port.
Otherwise, it consumes 2 block RAMs without using the parity bits.
Vivado Synthesis does not support parity bits for Asymmetric block RAM inference.
As a result you might see more block RAM utilization than expected when port width is 36 for asymmetric RAM.
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