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AR# 62030

ModelSim simulation of Zynq BFM throws error on non zero reset value.

Description

This error only happens with ModelSim.

Vivado Simulator does not exhibit the problem.

The version of ModelSim which is used is ModelSim SE-64 10.1c or ModelSim SE-64 10.2d. 

Example: I have a Zynq BFM with an interconnect on GP0 hooked to a peripheral in the fabric.

EMC_tb.JPG
EMC_tb.JPG


Running the BFM simulation in ModelSim produces the following error:

# [12] : M_AXI_GP0 : *ERROR : RVALID from slave is not zero (reset value) - AMBA AXI SPEC V2 - Section 11.1.2 Reset
# *** TEST FAILED

The BFM models are developed by Cadence and they have implemented some unwanted checks on resets.
To remove this check they have created an API.
 
set_disable_reset_value_checks(1);
 
There is a Zynq BFM developed by Xilinx, but internally it uses the cadence AXI BFMs to model each AXI port.
 
The Zynq BFM disables these reset checks by calling the API.

However, ModelSim occasionally does not apply the parameter at time 0 (instead it seems to apply a few delta cycles later).

The reset check is then operated by the BFM model, which leads to this error.
 

Below is the ModelSim log when running the simulation:

# [0] : *ZYNQ_BFM_INFO : M_AXI_GP0 : Port is ENABLED.
# [0] : M_AXI_GP0 : *INFO : Setting DISABLE_RESET_VALUE_CHECKS to 1
# BFM Xilinx: License succeeded for Xilinx_AXI_BFM, version 2010.100000
# **********************************************************
# * Cadence AXI 3 MASTER BFM                               *
# **********************************************************
# * VERSION NUMBER : 3.2.4
# **********************************************************
# * CONFIGURATION:
# * NAME = M_AXI_GP0
# * DATA_BUS_WIDTH = 32
# * ADDRESS_BUS_WIDTH = 32
# * ID_BUS_WIDTH = 12
# * MAX_OUTSTANDING_TRANSACTIONS = 16
# * EXCLUSIVE_ACCESS_SUPPORTED = 1
# * WRITE_BURST_DATA_TRANSFER_GAP = 0
# * RESPONSE_TIMEOUT = 500
# * DISABLE_RESET_VALUE_CHECKS = 0
# * WRITE_ID_ORDER_CHECK_FEATURE = 0
# * CLEAR_SIGNALS_AFTER_HANDSHAKE = 0
# * ERROR_ON_SLVERR = 0
# * ERROR_ON_DECERR = 0
# * STOP_ON_ERROR = 1
# * CHANNEL_LEVEL_INFO = 0
# * FUNCTION_LEVEL_INFO = 1

The error occurs on GP0.

Solution

If all input signals of the Zynq-BFM enabled BFM model(s) are checked at their expected reset value, the simulation will work.

There are two modifications to work around the problem:

1. The Zynq BFM asserts an internal reset at time 0 on all of its BFM interfaces.

The resets must not be active at time 0:

The workaround is to modify the file C:\Xilinx\Vivado\2014.2\data\ip\xilinx\processing_system7_bfm_v2_0\hdlprocessing_system7_bfm_v2_0_gen_reset.v as follows:

and change all of the reset values from 0 --> 1.
 

initial begin
r_m_axi_gp0_rstn = 1'b1;
r_m_axi_gp1_rstn = 1'b1;
r_s_axi_gp0_rstn = 1'b1;
r_s_axi_gp1_rstn = 1'b1;
r_s_axi_hp0_rstn = 1'b1;
r_s_axi_hp1_rstn = 1'b1;
r_s_axi_hp2_rstn = 1'b1;
r_s_axi_hp3_rstn = 1'b1;
r_s_axi_acp_rstn = 1'b1;
end


2. The testbench must NOT assert PS_PORB and PS_SRSTB for the first few clock cycles, this time is required by the AXI interconnect signals to "stabilize" to their reset values.
 
Approximately 5 to 6 clock cycles are necessary for an AXI BFM output signals to move from "X" to their reset value.

 Once these two modifications are applied, the log shows the following:

# [130] : M_AXI_GP0 : *INFO : Reset detected - setting output signals to reset values and checking input signals for correct reset values.
# [150] : M_AXI_GP0 : *INFO : Reset Checks Complete.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
62254 Zynq BFM simulation - Invalid release of reset. N/A N/A
AR# 62030
Date Created 09/12/2014
Last Updated 02/09/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2014.2
IP
  • AXI Bus Functional Model