The following error is observed when running write_bitstream to generate a bitfile using the External Master Configuration Clock (EMCCLK) for configuration of the 7 Series FPGA with SPI/BPI flash.
How can this issue be resolved?
The PACKAGE_PIN constraint should not be used.
Remove the PACKAGE_PIN constraint below from the XDC file:
The following attributes are common settings in the XDC file to allow for the use of EMCCLK.
This error is observed in Vivado 2014.2 and 2014.3 when the PACKAGE_PIN constraint is set in the XDC file.
In Vivado 2014.3/2014.2, the front end optimization tools ignore the PACKAGE_PIN constraint and do not create an input buffer when the signal is not used in the design.
It is not necessary to declare the EMCCLK input when the signal is not being used in the design and is only being used for configuration.
This issue is fixed in the 2015.1 release.
See (Xilinx Answer 44635) for additional EMCCLK details.