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AR# 62543

MIG UltraScale - Certain speed grades incorrectly prevent previously allowed input clock periods


Version Found: MIG UltraScale v6.0
Version Resolved: See (Xilinx Answer 58435)

Previously allowed input clock periods are no longer available in MIG GUI list for the input clock period even though all of the clocking requirements from (PG150) are met.

This behavior changed in MIG UltraScale 6.0 and is incorrect as the input clock requirements should not be
different across different speed grades targeting the same data rate.


To work around this issue the following MIG IP core parameters will need to be updated inside the <mig_core_name>_mig.sv module:

    parameter         CLKIN_PERIOD          = 13328,

    parameter         CLKFBOUT_MULT      = 16,        // write MMCM VCO multiplier

    parameter         DIVCLK_DIVIDE         = 1,        // write MMCM VCO divisor

    parameter         CLKOUT0_DIVIDE      = 4,        // VCO output divisor for MMCM clkout0

    parameter         CLKOUT1_DIVIDE      = 4,

    parameter         CLKOUT2_DIVIDE      = 4,

    parameter         CLKOUT3_DIVIDE      = 4,

    parameter         CLKOUT4_DIVIDE      = 4,

Note: Refer to (Xilinx Answer 57546) for information on how to modify/edit IP core source files in Vivado.

In order to determine the required parameter change values, the MULT/DIVIDE values can be determined using the Clocking Wizard from the IP Catalog.

Alternatively you can retarget a different speed grade and generate the input clock required and copy the parameter values over to the other design.

Revision History:

11/06/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 62543
Date 12/03/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Vivado Design Suite - 2014.3
  • MIG UltraScale