According to the Zynq Technical Reference Manual, you can set the target CPU for interrupt by configuring ICDIPTR registers.
This article includes an example targeting two AXI timers interrupts separately to cpu0 and cpu1.
This example is created targeting zc702 with Vivado 2014.2.
The steps to set up the example are as follows:
1. unzip the file, and generate the BD output and bitstream.
2. export hardware with bitstream and launch SDK.
3. import the BSPs and applications in the app folder into the workspace.
The BSP for cpu1 needs to be defined with USE_AMP=1.
In the example this is done by adding the flag "-DUSE_AMP" to extra_compiler_flags in the cpu1 BSP.
After this flag is added, the cpu1 application needs to be re-built.
When USE_AMP=1 is defined, the driver function DistInit(XScuGic *InstancePtr, u32 CpuID) will not configure these distributor registers of GIC, so only the cpu0 application configures the interrupt target CPU.
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