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AR# 62583

2014.x Vivado Simulator - xelab rangecheck may cause some IP cores to fail to elaborate by being too strict in handling VHDL null vectors

Description

When the rangecheck option is enabled for xelab in Vivado Simulator, a number of IP cores fail to elaborate with an error message similar to the following:

ERROR: [XSIM 43-3430] No value can belong to null range in file "d:/Work/Xilinx_Test_case/tst_top/tst_top.srcs/sources_1/ip/real_mult_18_18/mult_gen_v12_0/hdl/dsp.vhd" at line 1002

The use of a null vector is legal in VHDL, and is used in many IP cores to simplify highly generic code. 

Questa does not report this error, even with the -rangecheck switch added to vcom.

Some of the affected IP cores:

  • FFT
  • FIR Compiler
  • CIC Compiler
  • DFT
  • Multiplier


Solution

The -rangecheck option enables run time value range check for VHDL. 

You can disable this option to work around the issue.

The check for null vectors will be relaxed in Vivado 2015.1 and as a result the error will not occur in Vivado Simulator when -rangecheck is enabled.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 62583
Date Created 10/22/2014
Last Updated 03/16/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • More
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.4.1
  • Less
IP
  • Multiplier
  • Fast Fourier Transform
  • FIR Compiler
  • More
  • Cascaded Integrator Comb (CIC) Compiler
  • Discrete Fourier Transform
  • Less