Version Found: v3.1
Version Resolved and other Known Issues: See (Xilinx Answer 57945)
When simulating and synthesizing certain configurations of the UltraScale FPGA Gen3 Integrated Block for PCI Express v3.1 core example design, if VHDL is selected as the language in the core configuration GUI, it may fail due to syntax issues.
This is a known issue to be fixed in the next release of the core.
The following code changes are needed to work-around this issue:
In the source file pcie3_ultrascale_0.vhd <project_name/pcie3_ultrascale_0_example/pcie3_ultrascale_0.srcs/sources_1/ip/>, make the following changes:
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.
11/14/2014 - Initial Release