AR# 62670

UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List


This answer record lists the known issues and answer records associated with the Kintex/Virtex UltraScale FPGAs GTH Transceiver.



(Xilinx Answer 63026)UltraScale GTH Transceiver - Reference clock phase noise mask
(Xilinx Answer 65111)UltraScale RX/TXUSRCLK routing
(Xilinx Answer 64309)UltraScale GTH Transceiver: TX and RX latency values
(Xilinx Answer 64103)UltraScale GTH/GTY TX/RX PROG DIV block reset requirements
(Xilinx Answer 61723)UltraScale GTH and GTY transceivers reference clock AC coupling capacitor value
(Xilinx Answer 59834)My UltraScale device package is showing 2 power groups for the MGT power supplies when there is only one column of GTs
(Xilinx Answer 63704)UltraScale GTH/GTY - How to switch to use internal PRBS pattern generator when using Asynchronous Gearbox mode


(Xilinx Answer 57487)UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions
(Xilinx Answer 65228)How to share a COMMON block using GTH transceivers
(Xilinx Answer 64838)Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2
(Xilinx Answer 58437)Vivado - UltraScale Transceivers Wizard [Route 35-54] unrouted nets
(Xilinx Answer 62977)UltraScale GTH/GTY SATA COMINIT/COMAWAKE burst numbers are higher by 1
(Xilinx Answer 62548)My GTY/GTH refclk output is not toggling

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 62670
Date 09/03/2019
Status Active
Type Known Issues