We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63663

2014.4 Vivado Timing - Clock uncertainty shows up as "positive number" even when a negative value is applied


In the synthesized design of the example design "BFT Core", the following command returns a Clock uncertainty of 0.035ns:

report_timing -name test -from [get_clocks bftClk] -to [get_clocks bftClk]  -setup

When I try to set the Clock uncertainty to -0.100 and rerun the report_timing command, I find the Clock uncertainty is 0.065ns, even though it is expected to be -0.065ns.

set_clock_uncertainty -0.100 [get_clocks bftClk]
report_timing -name test -from [get_clocks bftClk] -to [get_clocks bftClk]  -setup

Is this only a display problem?



This is only a display issue in the GUI. The timing engine takes the correct UNCERTAINTY value in the path calculation.

If you check the "UNCERTAINTY" property of the timing path, you will find that the value is the expected negative value.

get_property UNCERTAINTY [get_timing_paths -from [get_clocks bftClk] -to [get_clocks bftClk] ]


This issue is fixed in the 2015.1 release of Vivado Design Suite.

AR# 63663
Date 03/04/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4