The UNIMACRO library is used in behavioral simulation when the RTL instantiates device macros.
See (UG953) Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide for a list of device macros.
The macros are bound to device primitives based on macro parameter settings.
Therefore in functional simulation, the UNISIM library is used instead.
VHDL UNIMACRO Library
The VHDL UNIMACRO library is located at <Vivado_Install_Dir>/data/vhdl/src/unimacro.
To use these macros, place the following two lines at the beginning of each file:
You must also compile the library and map the library to the simulator.
The method depends on the simulator.
Verilog UNIMACRO Library
The Verilog UNIMACRO library is located at <Vivado_Install_Dir>/data/verilog/src/unimacro.
In Verilog, the individual library modules are specified in separate HDL files.
This allows the -y library specification switch to search the specified directory for all components and automatically expand the library.
The Verilog UNIMACRO library does not need to be specified in the HDL file prior to using the module as is required in VHDL.
Verilog is case-sensitive, so ensure that UNIMACRO macro instantiations adhere to an uppercase naming convention, for example, BRAM_TDP_MACRO.
If you use precompiled libraries, use the correct simulator command-line switch to point to the precompiled libraries.
The following is an example for the Vivado simulator:
-L unimacro_ver -L unisims_ver
The UNISIM library is also pointed to because the UNIMACRO models instantiate the underlying UNISIM models.