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AR# 64088

Aurora Design Assistant - Core generation

Description

The Aurora Design Assistant walks you through the recommended design flow for Aurora 8B10B/ Aurora 64B66B designs while debugging commonly encountered issues, such as simulation issues, Initialization failures, and data errors.

The Design Assistant provides useful design and troubleshooting information, but also points you to the exact documentation you need to read to help you design efficiently with Aurora 8B10B/Aurora 64B66B.

Note: This Answer Record is a part of the Xilinx Aurora Solution Center (Xilinx Answer 21263).

The Xilinx Aurora Solution Center is available to address all questions related to Aurora 8B10B/Aurora 64B66B.

Whether you are starting a new design with Aurora or troubleshooting a problem, use the Aurora Solution Center to guide you to the right information.

Solution

  • For 7 series devices, please refer to (Xilinx Answer 53693) and (Xilinx Answer 53621) for the recommended core version to target IES/GES/production silicon.
     
  • If the Aurora core is used as a sub core in an embedded system design, it is recommended to generate the Aurora core with the "Little endian" option enabled.
    This option is available from the Vivado 2014.1 release on.

  • The "Customizing and Generating the Core" section in PG074/PG046 gives guidance on all of the fields in the GUI.

  • Choose the "Additional Transceiver debug ports" option for debug purposes only.
    If these ports are not handled properly, it can lead to incorrect functionality of the IP.

  • The "INIT_CLK" frequency provided in the GUI is used for some parameter calculations in the IP.
    It must provide the right frequency value when generating the core to ensure correct functionality.

  • From the Vivado 2015.1 release on, Aurora supports GT location selection from the GUI for UltraScale devices.
    For 2014.4 (or) earlier, it is recommended to ensure that the lane selection would start from Quad boundary.

  • Lanes must be consecutive in a multi-lane design.

  • From the Vivado 2015.1 release, both GT REFCLK and INIT_CLK can be set as "Single ended" when the "Shared logic in core" option is selected.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61912 Aurora Solution Center - Design Assistant N/A N/A
AR# 64088
Date Created 03/29/2015
Last Updated 07/01/2015
Status Active
Type Solution Center
IP
  • Aurora 64B/66B
  • Aurora 8B/10B