We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64223

Vivado IPI - AXI 1G/2.5G Ethernet Subsystem v6.2 or earlier - UltraScale SGMII over LVDS - idelay control element needs to be added manually for IPI design


When using AXI Ethernet in a Block Diagram (BD) design in "SGMII over LVDS" mode, I need to add an idelay control element manually.

How can I do this?


There is no idelay control element available in the IPI catalog and so you will need to add this as a local pcore.

Below are the steps to do this:

  1. Add the util_idelay control element as a local pcore
  2. Create the system as required in IPI.
  3. Add the idelay element in the IPI design
  4. Connect a 625MHz clock to the idelay control element.
  5. Instantiate a proc sys reset and generate a reset synchronous to the 625MHz clock, then connect it to the idelay control reset input
  6. Connect the rdy output port of the idelay control element to the AXI Ethernet idelay_rdy_in input port.

For earlier version of the core, additional steps are required. Please refer to (Xilinx Answer 64142).

This issue has been fixed in v7.0 of the AXI 1G/2.5G Ethernet Subsystem.

AR# 64223
Date 10/01/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
  • AXI Ethernet