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Xilinx Zynq UltraScale+ MPSoC Solution Center

The Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to the Zynq UltraScale+ MPSoC.

Whether you are starting a new design with Zynq UltraScale+ MPSoC or troubleshooting a problem, use the Zynq UltraScale+ MPSoC solution center to guide you to the right information.

QUICK LINKS:

Product Page

UltraScale Architecture and Product Overview

Design Assistant

Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller

This answer record helps you find all Zynq UltraScale+ MPSoC solutions related to the Processing System (PS) DDR Controller known issues.

Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.


General Guidance/Documentation

Xilinx Answer
Title
(Xilinx Answer 66193)
What are the limitations of the PS DDR controller? Which device should I choose?
(Xilinx Answer 67330)PS DDR Pin Swap Guidelines

Known issues

Xilinx AnswerTitleTool Version FoundTool Version Resolved (Planned)
(Xilinx Answer 65982)Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support2015.4(2016.1)
(Xilinx Answer 66571)Processor System IP GUI Limitations with PS DDR topologies2015.4(2016.1)

Design Advisories

Design Advisory Master Answer Record for Zynq UltraScale+ MPSoC Devices

The Zynq UltraScale+ MPSoC devices are documented in the Zynq data sheet, technical reference manual and other documents.

Important Design Advisories and other considerations that transcend these documents are listed here.

The source point for technical content is the Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).


Design Advisory Alerted on October 17th, 2016

(Xilinx Answer 67861)How do I upgrade from Vivado 2016.2 and earlier versions?

Design Advisory Alerted on April 18th, 2016

(Xilinx Answer 66944)Design Advisory for Zynq UltraScale+ MPSoC and Kintex UltraScale+ FPGA - Updated Package Pinouts