AR# 64452: Vivado Implementation - Error:[Place 30-574] Poor placement for routing between an I/O pin and BUFG
AR# 64452
Vivado Implementation - Error:[Place 30-574] Poor placement for routing between an I/O pin and BUFG
Description
The following error occurred during place_design:
ERROR:[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
and BUFG_inst (BUFG.I) is locked to BUFGCTRL_X0Y31
What does it mean and how do I resolve it?
Solution
This message is flagging a sub optimal routing connection between an I/O pin and BUFG.
This is because this I/O is not a clock capable pin and so there is no dedicated clock routing between the I/O and BUFG.
To resolve this issue, either:
1) Move the clock input to a clock capable pin.
or
2) Add the "CLOCK_DEDICATED_ROUTE" to the XDC as mentioned in the message if the I/O location is not able to be changed and the sub optimal route on local resources is acceptable.
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AR# 64452
Date
05/28/2015
Status
Active
Type
General Article
Tools
Vivado Design Suite
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