There are two known issues for UltraScale Architecture-based CPRI cores in the 2015.1 and 2015.2 versions.
They will be fixed in the 2015.3 release.
1. line 1003 in the file <cpri_core_name>_block.vhd :
It should be :
instead of :
This ensures that user_drp_dwe is assigned when drp_arb_gnt = '1'.
2. It is possible that speed capability could change when user DRP access is not completed.
The user DRP access will be cut off.
You will need to re-start the transition if you see the drp_arb_gnt go low before the ready was returned to them.
For other known issues for the CPRI core, please refer to (Xilinx Answer 54473)