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AR# 64739

CPRI v8.4 - Why do I see incorrect behavior when I use transceiver debug pins to access UltraScale DRP ports?


For CPRI v8.4, why do I see incorrect behavior when I use transceiver debug pins to access DRP ports?


There are two known issues for UltraScale Architecture-based CPRI cores in the 2015.1 and 2015.2 versions.

They will be fixed in the 2015.3 release.

1. line 1003 in the file <cpri_core_name>_block.vhd :

It should be :

user_drp_dwe => gt_drpwe_i,

instead of :

user_drp_dwe => gt_drpwe,

This ensures that user_drp_dwe is assigned when drp_arb_gnt = '1'.

2. It is possible that speed capability could change when user DRP access is not completed. 

The user DRP access will be cut off.

You will need to re-start the transition if you see the drp_arb_gnt go low before the ready was returned to them.

For other known issues for the CPRI core, please refer to (Xilinx Answer 54473)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54473 LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 64739
Date 06/30/2015
Status Active
Type General Article
  • CPRI
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