An enhancement in Vivado 2014.3 improves the power consumption at the BRAM primitive.
For the Block memory generator core in SPD mode with ECC, WEA is not used for a write operation any longer and ENA should be used instead.
However, this change has not been reflected in the behavioral simulation model.
As a result, the WEA port still works as in the earlier version of the core.
The model has been fixed in Vivado 2015.3.
As a work-around, WEA should be asserted with ENA for a write operation as described in Figure 3-30 of (PG058) April 1, 2015.