A small DC bias is seen in the spectrum at the output of the PC-CFR v6.0 core.
A small DC bias is seen at the output of the core in both "smart peak processing enabled" and "smart peak processing disabled" mode.
This is a result of using a specific type of rounding mode while generating the composite cancellation signal inside the PC-CFR core.
This has been fixed in PC-CFR v6.0 rev 2 in Vivado 2015.3 and the small DC bias is no longer seen in the PC-CFR output spectrum.
The fix has been tested in simulation as well as on board in a demo platform.
To resolve this issue, use PC-CFR v6.0 rev 2 available in Vivado 2015.3.