UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65421

UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbench

Description

Version Found: DDR3 v5.0

Version Resolved; See (Xilinx Answer 69036)

When running an UltraScale DDR3 simulation using the provided example_tb testbench, the memory model flags the following errors:

# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3151266.0 ps ERROR:   tIS violation on ADDR  4 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3151266.0 ps ERROR:   tIS violation on ADDR  6 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3151266.0 ps ERROR:   tIS violation on ADDR  8 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3176972.0 ps ERROR:   tIS violation on ADDR 10 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3703942.0 ps ERROR: CWL =           9 is illegal @tCK(avg) = 1071.076172
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3836756.0 ps ERROR:   tIS violation on BA 0    by 35.0 ps

Solution

The violation reported is that the address/bank is toggling at the rising edge of the DRAM clock, which the model reports as a tIS violation.

However, the model is flagging the violation on a DESELECT command which has "don't care" for address/bank.

These errors can be safely ignored.

Revision History:

09/30/2015Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 65421
Date 01/02/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.4.2
  • Vivado Design Suite - 2015.4.1
  • Vivado Design Suite - 2015.4
  • More
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Less
IP
  • MIG UltraScale
Page Bookmarked